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PD720201/ pd720202 assp (usb3.0 host controller) r19ds0047ej0500 rev. 5.00 page 1 of 40 jan. 17, 2013 data sheet r19ds0047ej0500 rev.5.00 jan. 17, 2013 1. overview the PD720201 and pd720202 are renesas? third generation univ ersal serial bus 3.0 host controllers, which comply with universal serial bus 3.0 specificat ion, and intel?s extensible host controller interface (xhci). these devices reduce power consumption and offer a smaller package foot-print making them ideal for designers who wish to add the usb3.0 interface to mobile computing devices such as laptops and notebook computers. the PD720201 supports up to four usb3.0 superspeed ports and the pd720202 supports up to two usb3.0 superspeed ports. the PD720201 and pd720202 use a pci express? gen 2 system interface bus allowing system designers to easily add up to four ( PD720201) or two ( pd720202) usb3.0 superspeed ports to systems containing the pci ex press bus interface. when connected to usb 3.0- compliant peripherals, the PD720201 and pd720202 can transfer informati on at clock speeds of up to 5 gbps. the PD720201 and pd720202 and usb3.0 standard are fully compliant and backward compatible with the previous usb2.0 standard. the new usb3.0 standard supports data transfer speeds of up to ten times faster than those of the prev ious-generation usb2.0 standard, enabling quick and efficient transfers of large amounts of information. 1.1 features z compliant with universal serial bus 3.0 specif ication revision 1.0, which is released by usb implementers forum, inc - supports the following speed data rate as follows: low-speed (1.5 mbps) / full-speed (12 mbps) / hi-speed (480 mbps) / superspeed (5 gbps) - PD720201 supports up to 4 downstream ports for all speeds - pd720202 supports up to 2 downstream ports for all speeds - supports all usb compliant data transfer types as follows; control / bulk / interrupt / isochronous transfer z compliant with intel?s extensible host contro ller interface (xhci) specification revision 1.0 - supports usb debugging capability on all superspeed ports. z supports usb legacy function z compliant with pci express ba se specification revision 2.0 z supports latency tolerance reporting ecn of pci express specification z supports expresscard tm standard release1.0 z supports pci express card electromechanical specification revision 2.0 z supports pci bus power management in terface specification revision 1.2 z supports usb battery charging specificati on revision 1.2 and other portable devices - dcp mode of bc 1.2 - cdp mode of bc 1.2 - china mobile phone chargers - eu mobile phone chargers - apple ios products z operational registers are direct-mapped to pci memory space z supports serial peripheral interf ace (spi) type rom for firmware z supports firmware download interface from system bios or system software z system clock: 24 mhz crystal
PD720201/ pd720202 1. overview r19ds0047ej0500 rev. 5.00 page 2 of 40 jan. 17, 2013 z small and low count pin package with improved signal pin assignment for efficient pcb layout - PD720201 adopts 68pin qfn (8 x 8) - pd720202 adopts 48pin qfn (7 x 7) z 3.3 v and 1.05 v power supply
PD720201/ pd720202 1. overview r19ds0047ej0500 rev. 5.00 page 3 of 40 jan. 17, 2013 1.2 applications desktop and laptop computers, tablet, server, pci express card / ex press card, digital tv, set-top-box, bd player/recorder, media player, digital audio system s, projector, multi function printer, storage, router, nas, etc 1.3 ordering information note PD720201k8-711-bac-a & pd720202k8-711-baa-a sh ould use the fw download function. PD720201k8-711-bac-a & pd720202k8-711-baa-a do not suppor t the external rom (serial peripheral interface (spi) type rom). PD720201 & pd720202 should download the firmware from the external rom (-701 versions only) or by fw download function after power on reset. regarding the external rom & fw download function, refer to ?6.how to acce ss external rom? & ?7. fw download interface? in the PD720201 & pd720202 user?s manual : r19uh0078e. part number package oper ating temperature remark PD720201k8-701-bac-a pd720202k8-701-baa-a 68-pin qfn (8 8) 48-pin qfn (7 x 7) 0 ~ 85 c lead-free product lead-free product PD720201k8-711-bac-a pd720202k8-711-baa-a 68-pin qfn (8 8) 48-pin qfn (7 x 7) -40 ~ 85 c lead-free product lead-free product
PD720201/ pd720202 1. overview r19ds0047ej0500 rev. 5.00 page 4 of 40 jan. 17, 2013 1.4 block diagram figure 1-1. PD720201 block diagram figure 1-2. pd720202 block diagram pci express gen2 interface complies with pci express gen2 interface, with 1 lane. this block includes both the link and phy layers. xhci controller handles all s upport required for usb 3.0, superspeed and hi-/full-/low-speed. this block includes the register interface from the system. root hub hub function in host controller. ss phy for superspeed tx/rx hs/fs/ls phy for hi-/ full-/low-speed tx/rx power sw i/f connected to external power switch for port power control and over current detection. spi interface connected to external serial rom. when system bios or system software does not support fw download function, the external serial rom is required. osc internal oscillator block.
PD720201/ pd720202 1. overview r19ds0047ej0500 rev. 5.00 page 5 of 40 jan. 17, 2013 1.5 pin configuration (top view) ? 68-pin qfn (8 8) PD720201k8-701-bac-a PD720201k8-711-bac-a figure 1-3. pin configuration of PD720201 u2dm4 u2dp4 vdd33 u3rxdn4 u3rxdp4 vdd10 u3txdn4 u3txdp4 vdd10 u2dm3 u2dp3 vdd33 u3rxdn3 u3rxdp3 vdd10 u3txdn3 u3txdp3 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 smib 1 51 u2dm2 perstb 2 50 u2dp2 pewakeb 3 49 vdd33 peclkp 4 48 u3rxdn2 peclkn 5 47 u3rxdp2 avdd33 6 46 vdd10 petxp 7 45 u3txdn2 petxn 8 44 u3txdp2 vdd10 9 gnd 43 vdd10 perxp 10 42 u2dm1 perxn 11 41 u2dp1 vdd10 12 40 vdd33 pecreqb 13 39 u3rxdn1 ponrstb 14 38 u3rxdp1 vdd33 15 37 vdd10 spiso 16 36 u3txdn1 spicsb 17 35 u3txdp1 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 spisck spisi oci4b ppon4 oci3b ppon3 oci2b ppon2 oci1b ppon1 vdd10 vdd33 xt2 xt1 avdd33 rref ic(l)
PD720201/ pd720202 1. overview r19ds0047ej0500 rev. 5.00 page 6 of 40 jan. 17, 2013 ? 48-pin qfn (7 x 7) pd720202k8-701-baa-a pd720202k8-711-baa-a figure 1-4. pin configuration of pd720202 pewakeb perstb smib u2dm2 u2dp2 vdd33 vdd10 u3rxdn2 u3rxdp2 vdd10 u3txdn2 u3txdp2 48 47 46 45 44 43 42 41 40 39 38 37 peclkp 1 36 u2dm1 peclkn 2 35 u2dp1 avdd33 3 34 vdd33 petxp 4 33 vdd10 petxn 5 32 u3rxdn1 vdd10 6 31 u3rxdp1 perxp 7 gnd 30 vdd10 perxn 8 29 u3txdn1 vdd10 9 28 u3txdp1 pecreqb 10 27 ic(l) ponrstb 11 26 rref vdd33 12 25 avdd33 13 14 15 16 17 18 19 20 21 22 23 24 spiso spicsb spisck spisi oci2b ppon2 oci1b ppon1 vdd10 vdd33 xt2 xt1
PD720201/ pd720202 2. pin function r19ds0047ej0500 rev. 5.00 page 7 of 40 jan. 17, 2013 2. pin function this section describes each pin functions. 2.1 power supply table 2-1. power supply pin name PD720201 pin no. pd720202 pin no. i/o type function vdd33 15, 29, 40, 49, 57, 66 12, 22, 34, 43 power +3.3 v power supply vdd10 9, 12, 28, 37, 43, 46, 54, 60, 63 6, 9, 21, 30, 33, 39, 42 power +1.05 v power supply. avdd33 6, 32 3, 25 power +3.3 v power supply for analog circuit. gnd gnd pad gnd pad power connect to ground. ic(l) 34 27 i test pin. connect to ground. 2.2 analog signal table 2-2. analog signal pin name 720201 pin no. 720202 pin no. i/o type active level function rref 33 26 usb2 ? reference resistor connection. 2.3 system clock table 2-3. system clock pin name 720201 pin no. 720202 pin no. type active level function xt1 31 24 i (osc) ? oscillator in connect to 24 mhz crystal. xt2 30 23 o (osc) ? oscillator out connect to 24 mhz crystal.
PD720201/ pd720202 2. pin function r19ds0047ej0500 rev. 5.00 page 8 of 40 jan. 17, 2013 2.3.1 system interface signal table 2-4. system interface signal pin name 720201 pin no. 720202 pin no. i/o type active level function ponrstb 14 11 i (3.3 v schmitt input) low power on reset signal. when supporting wakeup from d3cold, this signal should be pulled high with system auxiliary power supply. smib 1 46 o (open drain) low system management interrupt signal. this is controlled with the usb legacy support control/status register . refer to the user?s manual. 2.3.2 pci express interface table 2-5. pci express interface pin name 720201 pin no. 720202 pin no. i/o type active level function peclkp 4 1 i (pcie) ? pci express 100 mhz reference clock. peclkn 5 2 i (pcie) ? pci express 100 mhz reference clock. petxp 7 4 o (pcie) ? pci express transmit data+. petxn 8 5 o (pcie) ? pci express transmit data-. perxp 10 7 i (pcie) ? pci express receive data+. perxn 11 8 i (pcie) ? pci express receive data-. perstb 2 47 i (3.3 v input) low pci express ?perst#? signal. pewakeb 3 48 o (open drain) low pci express ?wake#? signal. this signal is used for remote wakeup mechanism, and requests the recovery of power and reference clock input. pecreqb 13 10 o (open drain) low pci express ?clkreq#? signal. this signal is used to request run/stop of reference clock.
PD720201/ pd720202 2. pin function r19ds0047ej0500 rev. 5.00 page 9 of 40 jan. 17, 2013 2.3.3 usb interface table 2-6. usb interface pin name 720201 pin no. 720202 pin no. i/o type active level function u3txdp1 35 28 o (usb3) ? usb3.0 transmit data d+ signal for superspeed u3txdn1 36 29 o (usb3) ? usb3.0 transmit data d- signal for superspeed u3rxdp1 38 31 i (usb3) ? usb3.0 receive data d+ signal for superspeed u3rxdn1 39 32 i (usb3) ? usb3.0 receive data d- signal for superspeed u2dp1 41 35 i/o (usb2) ? usb2.0 d + signal for hi-/full-/low-speed u2dm1 42 36 i/o (usb2) ? usb2.0 d ? signal for hi-/full-/low-speed oci1b 26 19 i (3.3 v input) low over-current status input signal. 0: over-current condition is detected 1: no over-current condition is detected ppon1 27 20 o (3.3 v output) high usb port power supply control signal. 0: power supply off 1: power supply on u3txdp2 44 37 o (usb3) ? usb3.0 transmit data d+ signal for superspeed u3txdn2 45 38 o (usb3) ? usb3.0 transmit data d- signal for superspeed u3rxdp2 47 40 i (usb3) ? usb3.0 receive data d+ signal for superspeed u3rxdn2 48 41 i (usb3) ? usb3.0 receive data d- signal for superspeed u2dp2 50 44 i/o (usb2) ? usb2.0 d + signal for hi-/full-/low-speed u2dm2 51 45 i/o (usb2) ? usb2.0 d ? signal for hi-/full-/low-speed oci2b 24 17 i (3.3 v input) low over-current status input signal. 0: over-current condition is detected 1: no over-current condition is detected ppon2 25 18 o (3.3 v output) high usb port power supply control signal. 0: power supply off 1: power supply on
PD720201/ pd720202 2. pin function r19ds0047ej0500 rev. 5.00 page 10 of 40 jan. 17, 2013 pin name 720201 pin no. 720202 pin no. i/o type active level function u3txdp3 52 ? o (usb3) ? usb3.0 transmit data d+ signal for superspeed u3txdn3 53 ? o (usb3) ? usb3.0 transmit data d- signal for superspeed u3rxdp3 55 ? i (usb3) ? usb3.0 receive data d+ signal for superspeed u3rxdn3 56 ? i (usb3) ? usb3.0 receive data d- signal for superspeed u2dp3 58 ? i/o (usb2) ? usb2.0 d + signal for hi-/full-/low-speed u2dm3 59 ? i/o (usb2) ? usb2.0 d ? signal for hi-/full-/low-speed oci3b 22 ? i (3.3 v input) low over-current status input signal. 0: over-current condition is detected 1: no over-current condition is detected ppon3 23 ? o (3.3 v output) high usb port power supply control signal. 0: power supply off 1: power supply on u3txdp4 61 ? o (usb3) ? usb3.0 transmit data d+ signal for superspeed u3txdn4 62 ? o (usb3) ? usb3.0 transmit data d- signal for superspeed u3rxdp4 64 ? i (usb3) ? usb3.0 receive data d+ signal for superspeed u3rxdn4 65 ? i (usb3) ? usb3.0 receive data d- signal for superspeed u2dp4 67 ? i/o (usb2) ? usb2.0 d + signal for hi-/full-/low-speed u2dm4 68 ? i/o (usb2) ? usb2.0 d ? signal for hi-/full-/low-speed oci4b 20 ? i (3.3 v input) low over-current status input signal. 0: over-current condition is detected 1: no over-current condition is detected ppon4 21 ? o (3.3 v output) high usb port power supply control signal. 0: power supply off 1: power supply on note 1 : the superspeed signals (u3txdpx, u3txdnx, u3 rxdpx, u3rxdnx) and high-/full-/low-signals (u2dpx, u2dmx) of PD720201 and pd720202 shall be connected to the same usb connecter, refer to PD720201/ pd720202 user?s manual. note 2 : the timing of pponx assertion is changed from pd720200. the pponx of pd720200a, PD720201 and pd720202 are asserted after the software sets max device slots enable(maxslotsen) field in configure(config) regi ster or host controller reset(hcrst) flag in usbcmd register. on pd720200, the ppon(2:1) are asserted im mediately after the pcie reset. regarding the config and usbcmd register, refer to the PD720201/ pd720202 user's manual.
PD720201/ pd720202 2. pin function r19ds0047ej0500 rev. 5.00 page 11 of 40 jan. 17, 2013 2.3.4 spi interface table 2-7. spi interface pin name 720201 pin no. 720202 pin no. type active level function spisck 18 15 o (3.3 v output) ? spi serial flash rom clock signal. when the external serial rom is not mounted, this signal should be pulled down through a pull- down resistor. spicsb 17 14 o (3.3 v output) ? spi serial flash rom chip select signal. when the external serial rom is not mounted, this signal should be pulled down through a pull- down resistor. spisi 19 16 o (3.3 v output) ? spi serial flash rom slave input signal. when the external serial rom is not mounted, this signal should be pulled down through a pull- down resistor. spiso 16 13 i (3.3 v input) - spi serial flash rom slave output signal. this signal should be pulled up through a pull-up resistor in all cases.
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 12 of 40 jan. 17, 2013 3. electrical specifications 3.1 buffer list ? 3.3 v input buffer oci(4:1)b, perstb, ic(l) ? 3.3 v input schmitt buffer ponrstb ? 3.3 v i olh = 4ma output buffer ppon(4:1) ? 3.3 v i ol = 4ma bi-directional buffer spiso, spisi, spisck, spicsb ? open drain buffer pewakeb, pecreqb, smib ? 3.3 v oscillator interface xt1, xt2 ? usb classic interface u2dp(4:1), u2dn(4:1), rref ? pci express serdes peclkp, peclkn, petxp, petxn, perxp, perxn ? usb superspeed serdes (serializer-deserializer) u3txdp(4:1), u3txdn(4:1), u3rxdp(4:1), u3rxdn(4:1)
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 13 of 40 jan. 17, 2013 3.2 terminology table 3-1. terms used in absolute maximum ratings parameter symbol meaning power supply voltage v dd33 , v dd10 , av dd33 indicates the voltage range within which damage or reduced reliability will not result when power is applied to a vdd pin. input voltage v i indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. output voltage v o indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. output current i o indicates absolute tolerance values for dc current to prevent damage or reduced reliability when current flows out of or into output pin. storage temperature t stg indicates the element temperatur e range within which damage or reduced reliability will not result while no voltage or current is applied to the device. table 3-2. terms used in recommended operating range parameter symbol meaning power supply voltage v dd33 , v dd10 , av dd33 indicates the voltage range for normal logic operations occur when gnd = 0 v. high-level input voltage v ih indicates the voltage, which is appli ed to the input pins of the device, is the voltage indicates that the hi gh level states for normal operation of the input buffer. * if a voltage that is equal to or greater than the ?min.? value is applied, the input voltage is gua ranteed as high level voltage. low-level input voltage v il indicates the voltage, which is appli ed to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * if a voltage that is equal to or lesser than the ?max.? value is applied, the input voltage is guar anteed as low level voltage. input rise time t ri indicates the limit value for the time period when an input voltage applied to the input pins of the device rises from 10% to 90%. input fall time t fi indicates the limit value for the time period when an input voltage applied to the input pins of the device falls from 90% to 10%. operating temperature t a indicates the ambient temperature range for normal logic operations. table 3-3. term used in dc characteristics parameter symbol meaning off-state output leakage current i oz indicates the current that flows from the power supply pins when the rated power supply voltage is appl ied when a 3-state output has high impedance. input leakage current i i indicates the current that flows when the input voltage is supplied to the input pin.
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 14 of 40 jan. 17, 2013 3.3 absolute maximum ratings table 3-4. absolu te maximum ratings parameter symbol condition rating units v dd33 , av dd33 ? 0.5 to + 4.6 v power supply voltage v dd10 ? 0.5 to + 1.4 v input voltage, 3.3 v buffer v i v i < v dd33 + 0.5 v ? 0.5 to + 4.6 v output voltage, 3.3 v buffer v o v o PD720201k8-701-bac-a, pd720202k8-701-baa-a) t a 0 + 85 c operating ambient temperature ( PD720201k8-711-bac-a, pd720202k8-711-baa-a) t a -40 + 85 c
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 15 of 40 jan. 17, 2013 3.5 dc characteristics table 3-6. dc characteristics parameter symbol condit ion min. max. units off-state output current i oz v i = v dd33 or gnd 10 a input leakage current i i v i = v dd33 or gnd 10 a low-level output voltage v ol i ol = 0ma 0.1 v high-level output voltage v oh i oh = 0ma v dd33 -0.1 v table 3-7. usb interface block parameter symbol condit ions min. max. unit output pin impedance z hsdrv 40.5 49.5 input levels for low-/full-speed: high-level input voltage (drive) v ih 2.0 v high-level input voltage (floating) v ihz 2.7 3.6 v low-level input voltage v il 0.8 v differential input sensitivity v di ? (d + ) ? (d ? ) ? 0.2 v differential common mode range v cm includes v di range 0.8 2.5 v output levels for low-/full-speed: high-level output voltage v oh rl of 14.25 k to gnd 2.8 3.6 v low-level output voltage v ol rl of 1.425 k to 3.6 v 0.0 0.3 v se1 v ose1 0.8 v output signal crossover point voltage v crs 1.3 2.0 v input levels for hi-speed: hi-speed squelch detection threshold (differential signal) v hssq 100 150 mv hi-speed disconnect detection threshold (differential signal) v hsdsc 525 625 mv hi-speed data signaling common mode voltage range v hscm ? 50 + 500 mv hi-speed differential input signaling level see figure 3-13 output levels for hi-speed: hi-speed idle state v hsoi ? 10 + 10 mv hi-speed data signaling high v hsoh 360 440 mv hi-speed data signaling low v hsol ? 10 + 10 mv chirp j level (differential signal) v chirpj 700 1100 mv chirp k level (differential signal) v chirpk ? 900 ? 500 mv
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 16 of 40 jan. 17, 2013 3.6 pin capacitance table 3-8. pin capacitance parameter symbol condit ion min. max. units spi interface pin capacitance c spi 5 pf 3.7 sequence for turning on or off power it is recommended that the time difference between t he start of power-supply rise (3.3v or 1.05v) and the point where both power supplies are st abilized should be within 100ms, regardless of the order of power source. a voltage of 0.1v dd has to be raised to 0.9v dd while the time difference is measured. figure 3-1. order of power source 3.3v 1.05v gnd within 100ms within 100ms 0.9v dd 0.1v dd 0.1v dd
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 17 of 40 jan. 17, 2013 3.8 ac characteristics 3.8.1 system clock table 3-9. system clock (xt1/xt2) ratings parameter symbol condition min. typ. max. units clock frequency f clk crystal ? 100 ppm 24 + 100 ppm mhz clock duty cycle t duty 40 50 60 % remark required accuracy of crystal or oscillator block in cludes initial frequency accuracy, the spread of crystal capacitor loading, supply volt age, temperature and aging, etc. 3.8.2 pci express reference clock table 3-10. pci express interface - refere nce clock (peclkp and peclkn) timings parameter symbol condit ion min. max. units rising edge rate t rise see figure 3-5 0.6 4.0 v/ns falling edge rate t fall see figure 3-5 0.6 4.0 v/ns differential input high voltage v ih see figure 3-8 + 150 mv differential input low voltage v il see figure 3-8 ? 150 mv absolute crossing point voltage v cross see figure 3-3 + 250 + 550 mv variation of v cross over all rising clock edge v cross delta see figure 3-4 + 140 mv ring-back voltage margin v rb see figure 3-8 ? 100 + 100 mv time before v rb is allowed t stable see figure 3-8 500 ps average clock period accuracy t period avg ? 300 + 2800 ppm absolute period (including jitter and spread spectrum) t period abs 9.847 10.203 ns cycle to cycle jitter v ccjitter 150 ps absolute max input voltage v max see figure 3-3 + 1.15 v absolute min input voltage v min see figure 3-3 ? 0.3 v duty cycle see figure 3-6 40 60 % rising edge rate (peclkp) to falling edge rate (peclkn) matching see figure 3-7 20 % clock source dc impedance z c-dc see figure 3-2 40 60
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 18 of 40 jan. 17, 2013 figure 3-2. pci express reference clock system measurement point and loading figure 3-3. pci express single-ended measurement points for absolute cross point and swing figure 3-4. pci express single-ended measu rement points for delta cross point figure 3-5. pci express single-ended measureme nt points for rise and fall time matching
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 19 of 40 jan. 17, 2013 figure 3-6. pci express differential measur ement points for duty cycle and period figure 3-7. pci express differential m easurement points for rise and fall time figure 3-8. pci express differential measurement points for ring-back
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 20 of 40 jan. 17, 2013 3.8.3 reset table 3-11. power on reset (ponrstb) timings parameter symbol condit ion min. max. units power on reset time t ponrst see figure 3-9 1 ms remarks 1. there is no order to power-on of v dd33 , av dd33 , av dd33 and v dd10 . 2. all power sources should be stable within 100 ms from the fastest rising edge of power sources. 3. ponrstb shall be de-asserted after all power sources and the system clock become stable. 4. ponrstb shall be de-asserted before de-asserting perstb. table 3-12. pci express interface - perstb signal timings parameter symbol condit ion min. max. units power stable to perstb inactive t pvperl see figure 3-9 100 ms peclkp/peclkn stable before perstb inactive t perst-clk see figure 3-9 100 s figure 3-9. power up and reset remark as a power saving feature, the PD720201 / pd720202 stops xt1/xt2 oscill ation whenever perstb is asserted (low) while ponrstb is inactive (high). xt1/xt2 oscillation does not stop while ponrstb is asserted (low).
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 21 of 40 jan. 17, 2013 3.8.4 pci express clkreq# table 3-13. pci express interface ? po wer-up and pecreqb signal timings parameter symbol condit ion min. max. units ponrstb inactive to pecreqb output active t pvcrl see figure 3-10 1 s table 3-14. pci express interface ? pecreqb clock control timings parameter symbol condit ion min. max. units pecreqb de-asserted high to clock parked t crhoff see figure 3-11 0 ns pecreqb asserted low to clock active t crlon see figure 3-11 400 ns figure 3-10. pci express power-up pecreqb timing figure 3-11. pci express pecreqb clock control timing power stable v dd33 & v dd10 ponrstb pecreqb peclkp peclkn ponrstb inactive t pvcrl
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 22 of 40 jan. 17, 2013 3.8.5 pci express interface ? differential transmitter (tx) specifications (refer to pci express base specification revision 2.0 for more information) table 3-15. pci express interface ? differe ntial transmitter (tx) specifications (1/2) parameter symbol 2.5gt/s 5.0gt/s. units unit interval ui 399.88(min) 400.12(max) 199.94(min) 200.06(max) ps differential peak to peak(p-p) tx voltage swing v tx-diffp-p 0.8(min) 1.2(max) 0.8(min) 1.2(max) v tx de-emphasis level ratio v tx-de-ratio-3.5db 3.0(min) 4.0(max) 3.0(min) 4.0(max) db tx de-emphasis level ratio v tx-de-ratio-6db not specified 5.5(min) 6.5(max) db instantaneous lone pulse width t min-pulse not specified 0.9(min) ui transmitter eye including all jitter sources t tx-eye 0.75(min) 0.75(min) ui maximum time between the jitter median and max deviation from the median t tx-eye-median-to- max-jitter 0.125(max) not specified ui tx deterministic jitter >1.5mhz t tx-hf-dj-dd not specified 0.15(max) ui tx rms jitter > 1.5mhz t tx-lf-rms not specified 3.0 ps rms transmitter rise and fall time t tx-rise-fall 0.125(min) 0.15(max) ui tx rise/fall mismatch t rf-mismatch not specified 0.1(max) ui maximum tx pll bandwidth b wtx-pll 22(max) 16(max) mhz minimum tx pll bw for 3db peaking b wtx-pll-lo-3db 1.5(min) 8(min) mhz minimum tx pll bw for 1db peaking b wtx-pll-lo-1db not specified 5(min) mhz tx pll peaking with 8mhz min bw p kgtx-pll1 not specified 3.0(max) db tx pll peaking with 5mhz min bw p kgtx-pll2 not specified 1.0(max) db tx package plus si differential return loss r ltx-diff 10(min) 10(min) for 0.05 ? 1.25ghz 8(min) for 1.25 ? 2.5ghz db tx package plus si common mode return loss r ltx-cm 6(min) 6(min) db dc differential tx impedance z tx-diff-dc 80(min) 120(max) 120(max)
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 23 of 40 jan. 17, 2013 (2/2) parameter symbol 2.5gt/s 5.0gt/s. units tx ac common mode voltage (5gt/s) v tx-cm-ac-pp not specified 100(max) mvpp tx ac common mode voltage (2.5gt/s) v tx-cm-ac-p 20 not specifed mv transmitter short-circuit current limit i tx-short 90(max) 90(max) ma transmitter dc common-mode voltage v tx-dc-cm 0(min) 3.6(max) 0(min) 3.6(max) v absolute delta of dc common mode voltage during l0 and electrical idle v tx-cm-dc-active- idle-delta 0(min) 100(max) 0(min) 100(max) mv absolute delta of dc common mode voltage between petxp and petxn v tx-cm-dc-line-delta 0(min) 25(max) 0(min) 25(max) mv electrical idle differential peak output voltage v tx-idle-diff-ac-p 0(min) 20(max) 0(min) 20(max) mv dc electrical idle differential output voltage v tx-idle-diff-dc not specified 0(min) 5(max) mv the amount of voltage change allowed during receiver detection v tx-rcv-detect 600(max) 600(max) mv minimum time spent in electrical idle t tx-idle-min 20(min) 20(min) ns maximum time to transition to a valid electrical idle after sending an eios t tx-idle-set-to-idle 8(max) 8(max) ns maximum time to transition to valid diff signaling after leaving electrical idle t tx-idle-to-diff-data 8(max) 8(max) ns crosslink random timeout t crosslink 1.0(max) 1.0(max) ns lane-to-lane output skew l tx-skew 500ps + 2ui(max) 500ps + 4ui(max) ps ac coupling capacitor c tx 75(min) 200(max) 75(min) 200(max) nf
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 24 of 40 jan. 17, 2013 3.8.6 pci express interface ? differential receiver (rx) specifications (refer to pci express base specification revision 2.0 for more information) table 3-16. pci express interface ? diffe rential receiver (rx) specifications (1/2) parameter symbol 2.5gt/s 5.0gt/s. units unit interval ui 399.88(min) 400.12(max) 199.94(min) 200.06(max) ps differential rx peak-peak voltage for common reference clock rx architecture v rx-diff-pp-cc 0.175(min) 1.2(max) 0.120(min) 1.2(max) v differential rx peak-peak voltage for data clocked rx architecture v rx-diff-pp-dc 0.175(min) 1.2(max) 0.100(min) 1.2(max) v receiver eye time opening t rx-eye 0.40(min) not specified ui max rx inherent timing error t rx-tj-cc not specified 0.40(max) ui max rx inherent timing error t rx-tj-dc not specified 0.34(max) ui max rx inherent deterministic timing error t rx-dj-dd-cc not specified 0.30(max) ui max rx inherent deterministic timing error t rx-dj-dd-dc not specified 0.24(max) ui max time delta between median and deviation from median t rx-eye-median-to-max- jitter 0.3(max) not specified ui minimum width pulse at rx t rx-min-pulse not specified 0.6(min) ui min/max pulse voltage on consecutive ui t rx-max-min-ratio not specified 5(max) - maximum rx pll bandwidth b wrx-pll-hi 22(max) 16(max) mhz minimum rx pll bw for 3db peaking b wrx-pll-lo-3db 1.5(min) 8(min) mhz minimum rx pll bw for 1db peaking b wrx-pll-lo-1db not specified 5(min) mhz rx pll peaking with 8 mhz min bw p kgrx-pll1 not specified 3.0 db rx pll peaking with 5mhz min bw p kgrx-pll2 not specified 1.0 db rx package plus si differential return loss r lrx-diff 10(min) 10(min) for 0.05 ? 1.25ghz 8(min) for 1.25 ? 2.5ghz db common mode rx return loss r lrx-cm 6(min) 6(min) db receiver dc single ended impedance z rx-dc 40(min) 60(max) 40(min) 60(max) dc differential impedance z rx-diff-dc 80(min) 120(max) not specified
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 25 of 40 jan. 17, 2013 (2/2) parameter symbol 2.5gt/s 5.0gt/s. units rx ac common mode voltage v rx-cm-ac-p 150(max) 150(max) mvp dc input cm input impedance for v>0 during reset or power down z rx-high-imp-dc-pos 50k(min) 50k(min) dc input cm input impedance for v<0 during reset or power down z rx-high-imp-dc-neg 1.0k(min) 1.0k(min) electrical idle detect threshold v rx-idle-det-diffp-p 65(min) 175(max) 65(min) 175(max) mv unexpected electrical idle enter detect threshold integration time t rx-idle-det-diff- entertime 10(max) 10(max) ms lane to lane skew l rx-skew 20(max) 8(max) ns
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 26 of 40 jan. 17, 2013 3.8.7 usb3.0 superspeed interface ? diff erential transmitter (tx) specifications (refer to universal serial bus 3.0 specif ication revision 1.0 for more information) table 3-17. transmitter no rmative electrical parameters parameter symbol min max units unit interval ui 199.94 200.06 ps differential p-p tx voltage swing v tx-diff-pp 0.8 1.2 v tx de-emphasis v tx-de-ratio 3.0 4.0 db dc differential impedance r tx-diff-dc 72 120 the amount of voltage change allowed during receiver detection v tx-rcv-detect 0.6 v ac coupling capacitor c ac-coupling 75 200 nf maximum slew rate t cdr-slew-max 10 ms/s table 3-18. transmitter info rmative electrical parameters parameter symbol min max units deterministic min pulse t min-pulse-dj 0.96 ui tx min pulse t min-pulse-tj 0.90 ui transmitter eye t tx-eye 0.625 ui tx deterministic jitter t tx-dj-dd 0.205 ui tx input capacitance for return loss c tx-parasitic 1.25 pf transmitter dc common mode impedance r tx-dc 18 30 transmitter short-circuit current limit i tx-short 60 ma transmitter dc common-mode voltage v tx-dc-cm 0 2.2 v tx ac common mode voltage v tx-cm-ac-pp-active 100 mvp-p absolute dc common mode voltage between u1 and u0 v tx-cm-dc-active- idle-delta 200 mv electrical idle differential peak- peak output voltage v tx-idle-diff-ac-pp 0 10 mv dc electrical idle differential output voltage v tx-idle-diff-dc 0 10 mv
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 27 of 40 jan. 17, 2013 3.8.8 usb3.0 superspeed interface ? diff erential receiver (rx) specifications (refer to universal serial bus 3.0 specif ication revision 1.0 for more information) table 3-19. receiver norm ative electrical parameters parameter symbol min max units unit interval ui 199.94 200.06 ps receiver dc common mode impedance r rx-dc 18 30 dc differential impedance r rx-diff-dc 72 120 dc input cm input impedance for v>0 during reset of power down z rx-high-imp-dc-pos 25k lfps detect threshold v rx-lfps-det-diff-p-p 100 300 mv table 3-20. receiver info rmative electrical parameters parameter symbol min max units differential rx peak-to-peak voltage v rx-diff-pp-post-eq 30 mv max rx inherent timing error t rx-tj 0.45 ui max rx inherent deterministic timing error t rx-dj-dd 0.285 ui rx input capacitance for return loss c rx-parasitic 1.1 pf rx ac common mode voltage v rx-cm-ac-p 150 mvpeak rx ac common mode voltage during the u1 to u0 transition v rx-cm-dc-active-idle- delta-p 200 mvpeak
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 28 of 40 jan. 17, 2013 3.8.9 usb2.0 interface (refer to universal serial bus specificat ion revision 2.0 for more information) table 3-21. low-speed sour ce electrical characteristics parameter symbol min max units driver characteristics: transition time: rise time fall time t lr t lf 75 75 300 300 ns ns rise and fall time matching t lrfm 80 125 % clock timings: low-speed data rate t ldraths 1.49925 1.50075 mb/s low-speed data timing: source jitter for differential transition to se0 transition t ldeop ? 40 100 ns source jitter total (including frequency tolerance): to next transition for paired transitions t ddj1 t ddj2 ? 25 ? 14 25 14 ns ns differential receiver jitter: to next transition for paired transitions t ujr1 t ujr2 ? 152 ? 200 152 200 ns ns source se0 interval of eop t leopt 1.25 1.50 s receiver se0 interval of eop t leopr 670 ns width of se0 interval during differential transition t lst 210 ns
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 29 of 40 jan. 17, 2013 table 3-22. full-speed sour ce electrical characteristics parameter symbol min max units driver characteristics: rise time t fr 4 20 ns fall time t ff 4 20 ns differential rise and fall time matching t frfm 90 111.11 % clock timings: full-speed data rate t fdraths 11.9940 12.0060 mb/s frame interval t frame 0.9995 1.0005 ms consecutive frame interval jitter t rfi 42 ns full-speed data timing: source jitter for differential transition to se0 transition t fdeop ? 2 5 ns source jitter total (including frequency tolerance): to next transition for paired transitions t dj1 t dj2 ? 3.5 ? 4 3.5 4 ns ns receiver jitter: to next transition for paired transitions t jr1 t jr2 ? 18.5 ? 9 18.5 9 ns ns source se0 interval of eop t feopt 160 175 ns receiver se0 interval of eop t feopr 82 ns width of se0 interval during differential transition t fst 14 ns
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 30 of 40 jan. 17, 2013 table 3-23. hi-speed sour ce electrical characteristics parameter symbol min max units driver characteristics: rise time (10% - 90%) t hsr 500 ps fall time (10% - 90%) t hsf 500 ps driver waveform requirements see figure 3-15 clock timings: hi-speed data rate t hsdrat 497.760 480.240 mb/s microframe interval t hsframe 124.9375 125.0625 s consecutive microframe interval difference t hsrfi 4 hi-speed bit times hi-speed data timing: data source jitter see figure 3-15 receiver jitter tolerance see figure 3-13 table 3-24. hub event timings parameter symbol min max units time to detect a downstream facing port connect event t dcnn 2.5 2000 s time to detect a disconnect event at a hub?s downstream facing port t ddis 2 2.5 s duration of driving resume to a downstream port t drsmdn 20 ms time from detecting downstream resume to rebroadcast t ursm 1.0 ms inter-packet delay for packets traveling in same direction t hsipdsd 88 bit times inter-packet delay for packets traveling in opposite direction t hsipdod 8 bit times inter-packet delay for root hub response for hi-speed t hsrspipd1 192 bit times time for which a chirp j or chirp k must be continuously detected by hub during reset handshake t filt 2.5 s time after end of device chirp k by which hub must start driving first chirp k in the hub?s chirp sequence t dchbit 100 s time for which each individual chirp j or chirp k in the chirp sequence is driven downstream by hub during reset t dchbit 40 60 s time before end of reset by which a hub must end its downstream chirp sequence t dchse0 100 500 s
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 31 of 40 jan. 17, 2013 figure 3-12. differential input sens itivity range for low-/full-speed 4.6 ? 1.0 input voltage range (v) differential input voltage range differential output crossover voltage range 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 figure 3-13. receiver sensitivit y for transceiver at u2dp/u2dm 0 v differential + 400 mv differential ? 400 mv differential unit interval level 1 level 2 0% 100% point 5 point 2 point 1 point 3 point 4 point 6 figure 3-14. receiver measurement fixtures vbus d + d ? gnd 15.8 + to 50 inputs of a high speed differential oscilloscope, or 50 outputs of a high speed differential data generator ? 50 coax 50 coax usb connector nearest device test supply voltage 15.8 143 143
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 32 of 40 jan. 17, 2013 figure 3-15. transmit wavefo rm for transceiver at u2dp/u2dm 0 v differential + 400 mv differential ? 400 mv differential unit interval level 1 level 2 0% 100% point 4 point 3 point 1 point 2 point 5 point 6 figure 3-16. transmitter measurement fixtures vbus d + d ? gnd 15.8 + to 50 inputs of a high speed differential oscilloscope, or 50 outputs of a high speed differential data generator ? 50 coax 50 coax usb connector nearest device test supply voltage 15.8 143 143 figure 3-17. differential data jitter for low-/full-speed
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 33 of 40 jan. 17, 2013 figure 3-18. differential-to-eop transiti on skew and eop width for low-/full-speed figure 3-19. receiver jitter tolerance for low-/full-speed
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 34 of 40 jan. 17, 2013 3.8.10 spi type serial rom interface table 3-25. spi type serial rom interface signals ti ming (spi mode 0) parameter symbol min. max. units spisck clock frequency 1 20 mhz clock pulses width low t scllow 25 ns clock pulses width high t sclhigh 25 ns spicsb disable time t scsdis 100 ns spicsb setup time t scssu 25 ns spicsb hold time t scsh 20 ns spisi setup time to spisck rising edge t sdwsu 6 ns spisi hold time from spisck rising edge t sdwh 6 ns spiso validate time from spisck falling edge t sdrvalid 25 ns spiso hold time from spisck falling edge t sdrh 0 ns spiso pull-up time from spicsb disabled (note) t srdet 170 ns note ?spiso disable time from spicsb disabled [t sdrdis ]? is expanded including ?spiso pull-up time [t srdet ]? as of rev5.00. this specification must be met only if PD720201 and pd720202 aborts firmware loading by pcie reset.
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 35 of 40 jan. 17, 2013 figure 3-20. spi type se rial rom signal timing figure 3-21. spiso pull-up timing from spicsb disabled
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 36 of 40 jan. 17, 2013 3.9 power consumption table 3-26. power consumption of PD720201 parameter device connection condition vdd10 line vdd33 line avdd33 line units there is no device on the ports under the l1 condition. 10 0.4 1.0 ma no device there is no device on the ports under the l0 condition. 150 3 22 ma only one device is connected on the port. low-speed data transfer on the port. 30 3 10 ma full-speed data transfer on the port. 140 3 22 ma hi-speed data transfer on the port. 150 35 22 ma 1 device superspeed transfer on the port. 430 3 32 ma two devices are connected on the ports. low-speed data transfer on the both ports. 40 3 10 ma full-speed data transfer on the both ports. 160 4 22 ma hi-speed data transfer on the both ports. 150 43 22 ma 2 devices superspeed transfer on the both ports. 520 3 32 ma three devices are connected on the ports. low-speed data transfer on the three ports. 40 3 10 ma full-speed data transfer on the three ports. 170 5 22 ma hi-speed data transfer on the three ports. 150 48 22 ma 3 devices superspeed transfer on the three ports. 610 3 32 ma four devices are connected on the ports. low-speed data transfer on the four ports. 40 3 11 ma full-speed data transfer on the four ports. 180 6 22 ma hi-speed data transfer on the four ports. 150 55 22 ma 4 devices superspeed transfer on the four ports. 700 3 32 ma 4 ss hubs with ss and hs devices four superspeed hub ar e connected on the all ports under ss and hs data transfer. 710 57 32 ma power consumption during system sleep condition. (wake on connect, wake on disconnect and wake on over-current are disabled.) 0.9 0.3 0.1 ma no device (d3-cold) power consumption during system sleep condition. (wake on connect, wake on disconnect and/or wake on over-current are enabled.) 3.4 0.3 1.0 ma power consumption ls device (d3-cold) power consumption during system sleep condition with one ls device enabling the remote wakeup function. 2.9 0.3 0.1 ma typical condition (t a = 25 c, v dd33 = 3.3 v, v dd10 = 1.05 v), operating pci express gen2 system.
PD720201/ pd720202 3. electric al specifications r19ds0047ej0500 rev. 5.00 page 37 of 40 jan. 17, 2013 table 3-27. power consumption of pd720202 parameter device connection condition vdd10 line vdd33 line avdd3 3 line units there is no device on the ports under the l1 condition. 8 0.2 1.0 ma no device there is no device on the ports under the l0 condition. 150 3 22 ma only one device is connected on the port. low-speed data transfer on the port. 30 2 10 ma full-speed data transfer on the port. 130 3 22 ma hi-speed data transfer on the port. 140 35 22 ma 1 device superspeed transfer on the port. 360 2 32 ma two devices are connected on the ports. low-speed data transfer on the both ports. 30 2 11 ma full-speed data transfer on the both ports. 150 3 22 ma hi-speed data transfer on the both ports. 140 43 22 ma 2 devices superspeed transfer on the both ports. 450 2 32 ma 2 ss hubs with ss and hs devices two superspeed hub are connected on the both ports under ss and hs data transfer. 460 42 32 ma power consumption during system sleep condition. (wake on connect, wake on disconnect and wake on over-current are disabled.) 0.7 0.1 0.1 ma no device (d3-cold) power consumption during system sleep condition. (wake on connect, wake on disconnect and/or wake on over-current are enabled.) 2.2 0.1 0.9 ma power consumption ls device (d3-cold) power consumption during system sleep condition with one ls device enabling the remote wakeup function. 1.8 0.1 0.1 ma typical condition (t a = 25 c, v dd33 = 3.3 v, v dd10 = 1.05 v), operating pci express gen2 system.
PD720201/ pd720202 4. package drawings r19ds0047ej0500 rev. 5.00 page 38 of 40 jan. 17, 2013 4. package drawings ? PD720201k8-701-bac-a ? PD720201k8-711-bac-a 68-pin qfn (8x8)
PD720201/ pd720202 4. package drawings r19ds0047ej0500 rev. 5.00 page 39 of 40 jan. 17, 2013 ? pd720202k8-701-baa-a ? pd720202k8-711-baa-a 48-pin qfn (7x7)
PD720201/ pd720202 5. recommended soldering conditions r19ds0047ej0500 rev. 5.00 page 40 of 40 jan. 17, 2013 5. recommended soldering conditions the PD720201 and pd720202 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact a renesas electronics sales representative. for technical information, see the following website. semiconductor device mount manual (h ttp://www.renesas.com/prod/package/manual/ ) ? PD720201k8-701-bac-a : 68-pin qfn (8x8) ? pd720202k8-701-baa-a : 48-pin qfn (7x7) ? PD720201k8-711-bac-a : 68-pin qfn (8x8) ? pd720202k8-711-baa-a : 48-pin qfn (7x7) soldering method solder ing conditions symbol infrared reflow peak package?s surface temperat ure: 260c, reflow time: 60 seconds or less (220c or higher), maximum allowable number of reflow processes: 3, exposure limit note : 7 days (10 hours pre-backing is required at 125c afterwards), flux: rosin flux with low chlori ne (0.2 wt% or below) recommended. non-heat-resistant trays, such as m agazine and taping trays, cannot be baked before unpacking. ir60-107-3 note the maximum number of days during which the product c an be stored at a temperatur e of 25c and a relative humidity of 65% or less after dry-pack package is opened.
all trademarks and registered trademarks are t he property of their respective owners. c - 1 revision history PD720201/ pd720202 data sheet description rev. date page summary 0.01 dec. 7, 2010 - first edition issued 0.02 apr. 21, 2011 - z chapter1 ? updated ordering information. z chapter2 ? updated table 5-1. spi interface z chapter4 ? updated package information. 0.03 june 6, 2011 - z chapter 1 ? changed the revision of usb battery charging specification z chapter 5 ? updated the recommended soldering condition information 0.04 september 16, 2011 - z chapter 1 ? updated the section 1.2 applications z chapter 2 ? modified the misdescription of smib (i/o type) of table 2-4. system interface signal. z chapter 3 ? updated the spi type serial rom interface ? updated the power consumption 1.00 september 26, 2011 - z document promoted from preliminary data to full data. (document no. r19ds0047e) z chapter 3 ? modified the misdescription ocixb of the section 3.1 buffer list 2.00 march 2, 2012 - z chapter 1 ? modified the typo of part number of section 1.5 pin configuration z chapter 2 ? changed the function of spiso of table 2-7. spi interface
all trademarks and registered trademarks are t he property of their respective owners. c - 2 description rev. date page summary 3.00 may 25, 2012 - z chapter 1 ? updated 1.3 ordering information ? updated 1.5 pin confi guration (top view) z chapter 3 ? updated the operating temperature table 3-5. recommended operating ranges ? deleted the condition of table 3-6. dc characteristics ? deleted the condition of table 3-9. system clock (xt1/xt2) ratings ? deleted the condition of table 3-11. power on reset (ponrstb) timings ? change the parameter name & value of table 3-13. pci express interface -power-up and pecreqb signal timings ? added the remark to figure 3-9. power up and reset z chapter 4 ? added the part number z chapter 5 ? added the part number 4.00 september 20, 2012 - z chapter 3 ? deleted the description of section 3.9 5.00 january 17, 2013 z chapter 1 ? updated 1.1 features ? added ?note? to 1.3 ordering information z chapter 3 ? updated table3-25 spi type serial rom interface signals timing (spi mode 0) ? added figure 3-21 spiso pull-up timing from spicsb disabled z all chapters ? modified the typo
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"standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactu re, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. htt p ://www.renesas.co m refer to "htt p ://www.renesas.com/" for the latest and detailed information . r e n esas el ec tr o ni cs am e ri ca in c . 2880 scott boulevard santa clara , ca 95050-2554 , u.s.a . tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-651-700, fax: +44-1628-651-804 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics mala y sia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petalin g jaya, selan g or darul ehsan, malaysi a tel: +60-3-7955-9390 , fax: +60-3-7955-951 0 renesas electronics korea co. , ltd . 11f., samik lavied' or bld g ., 720-2 yeoksam-don g , kan g nam-ku, seoul 135-080, korea tel: +82-2-558-3737 , fax: +82-2-558-514 1 s ale s o ffi c e s ? 2012 renesas electronics corporation. all ri g hts reserved . colo p hon 2.2

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